Matthias Gries

Postal Address

Huawei Technologies
German Research Center (GRC)
Riesstr. 25
80992 München, Germany

WWW

http://www.mgries.net

E-mail

I joined Huawei Technologies' Advanced Computing team in München, Germany, in June 2015. From 2007 to 2014, I developed integrated hardware-software technologies for memory subsystems, manycore, and resource management at Intel in Braunschweig, Germany. Before, at Infineon Technologies in Munich, Germany, I developed programmable microarchitectures and their programming views for network applications at the Corporate Research and Communication Solutions departments. I was a post-doctoral researcher in the Mescal group at UC Berkeley from 2002 to 2004 working on methods for ASIP design. I received my Ph.D. ("Dr. sc. techn." to be precise) from ETH Zurich, Switzerland, in 2001 for my work on QoS network processors. My interests include architectures, methods and tools for developing x86 platforms, ASIPs, system-level design, and analysis of MP-SoCs.

Overview

Projects

at Huawei Technologies [since 2015, Munich, Germany]: memory subsystem design for scientific computing and data centers (SoC digital design, performance evaluation, competitive analysis)
at Intel GmbH [2007 - 2014, Braunschweig, Germany]: persistent memory/NVM, Single-chip Cloud Computer, power management
at Infineon Technologies AG [2004 - 2007, Munich, Germany]: Network Optimized Versatile Architecture SoC, code generation
at UC Berkeley [2002 - 2004] : architecture development framework for ASIPs
at ETH Zurich [1997 - 2001]: IP packet processor

Curriculum Vitae
Publications
Older stuff: teaching assistance

Software

Persistent Memory: exposing Non-Volatile Memory (NVM) as durable random access memory to applications; Intel Labs, complemented by NOVOS project at TU Cottbus (link to page at BTU), 2012 - '14
SystemClick: SystemC and CRACC combined for design space exploration at Infineon (see DAC'08 paper)
CRACC embedded software development framework at Infineon (see DAC'05 paper)
Tipi: Mescal architecture development system at UC Berkeley (2004)
EXPO (page at ETH Zürich): Design space exploration tool at ETH Zurich (2001)
DRAM models for SimpleScalar CPU micro-architecture simulator, at ETH Zurich (2000)

Hardware

In-system prototyping with QPI-FPGA for mixed DRAM - NVM (such as Phase Change and Spin-Transfer Torque memories) subsystems, Intel Labs, 2012 - '14
Realtime DDR3 Programmable Memory Traffic Analyzer, Intel Labs, FPGA-based prototype (see Intel's press kit for the Research@Intel Europe event 2011, demonstration in computing zone)
Single-chip Cloud Computer (SCC), Intel Labs, 45nm silicon experimental processor (see ISSCC'10 paper "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS" aka. Single-chip Cloud Computer [SCC])
Network Optimized Versatile Architecture (NOVA), Infineon Technologies, FPGA prototype (see DATE'07 paper and CeBIT'06 trade fair demonstration)
Book on Mescal methodology for ASIP design, UC Berkeley, 2005

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