since 06/2015

Huawei Technologies Duesseldorf GmbH, Munich Research Center (MRC), Germany - principal engineer.
Since 2020: Advanced Computing, HiSilicon branch: Ecosystem enabling for HiSilicon Kunpeng Arm AArch64 and Ascend AI/ML processors.
HPC / Arm SVE / scientific computing software enabling, performance characterization, architecture evaluation on real hardware and by architecture simulation (gem5 & internal simulators).

2019: Automotive Engineering Lab, HiSilicon branch: Feasibility of HiSilicon Kunpeng and Ascend IP in automotive designs.

2015-'18, Advanced Computing, Central Hardware Dept.: Concept design and evaluation of near-data processing on memory modules (DDR4/DDR5 DIMM-NDP), memory and ARMv8 subsystem design (high bandwidth [HBM, GDDR] and non-volatile memory [PCM, 3DX, Flash]) for scientific computing and data centers with focus on SoC digital design, performance engineering and competitive analysis (ARMv8 and x86).

02/2015 - 05/2015

Roche Diagnostics GmbH, Diabetes Care R&D, Mannheim, Germany - senior systems engineer.
Systems engineering of medical cyberphysical systems (incl. software stack on MP-SoCs) for personal health care.

04/2007 - 12/2014

Intel GmbH, Germany Microprocessor Lab, Braunschweig - senior research scientist.
Systems Technology Lab; since June'09 Microprocessor and Programming Research.
Hardware-software integration of memory hierarchy (with non-volatile memory [PCM, STT, 3DXPoint], and high-bandwidth memory [DDR3, HBM, GDDR5]), platform resource management (app-driven DVFS, load balancing), Single-chip Cloud Computer (SCC) experimental manycore x86 chip implementation, test and performance characterization.

07/2004 - 03/2007

Infineon Technologies, Corporate Research + Communication Solutions departments, Munich, Germany - research engineer.
Networked systems & processor architectures.
Benchmark definition and implementation, design of SoC components for multiprocessor platform, implementation of programming models for embedded platforms.

05/2002 - 06/2004

University of California at Berkeley, CAD group, Prof. Kurt Keutzer - post-doc researcher.
Mescal project, funded by GSRC and Infineon Technologies.
Methods for design space exploration of network processor architectures and system software, as well as ASIP design. 

02/1997 - 04/2002

ETH Zürich, Computer Engineering and Networks Laboratory, Switzerland - research assistant.
IP Cube project with Inalp Networks on QoS in network processors, funded by the Swiss Commission for Technology and Innovation (KTI).
Teaching assistant for classes on Hardware-Software Codesign, Computer Architecture, Operating Systems, and Embedded Systems Design.

02/1997 - 05/2001

Ph.D. (Doctor of Technical Sciences) ETH Zürich, Computer Engineering and Networks Laboratory, Switzerland.
Advisors: Prof. Lothar Thiele, Prof. Wolfgang Fichtner
Thesis: Algorithm-Architecture Trade-offs in Network Processor Design.

10/1991 - 12/1996

Dipl.-Ing. degree (M.Sc. equivalent) in Electrical Engineering, Technical University of Hamburg-Harburg (TUHH), Germany.
Thesis: Reconfigurable Computer Architectures for the Video Codec ITU H.263.
Studies of Electrical Engineering with focus on digital signal processing (communications).