Algorithm-Architecture Trade-offs in Network Processor Design

Matthias Gries, PhD thesis, ETH Zurich, Switzerland, ETH Diss No 14191, May 2001

The increasing use of computer networks for all kinds of information exchange between autonomous computing resources is associated with a number of side-effects. In the Internet, where computers all over the globe are interconnected, the traffic volume grows faster than the infrastructure improves, leading to congestion of networking routes. In the application domain of embedded systems, networks can be used to couple complex sensor systems with a computing core. The provision of raw bandwidth may not be sufficient in such systems to allow control with real-time constraints. The underlying requirement in both cases is a network service with a defined quality, for instance, in terms of traffic loss ratio and worst-case communication delay. The provision of suitable communication services however requires a noticeable overhead in terms of computing load. Therefore, application-specific hardware accelerators - so-called network processors - have been introduced to speed up or even enable the maintenance of certain network services. The following issues have not yet been dealt with:

The above issues are addressed in this thesis and the major contributions in the research area of algorithms and architectures for network processors are:

Keywords: network processors, packet processing (queuing, scheduling), system-level design, memory controller/DRAM functionality

Keywords: network processing, policing, queue management, scheduling, design space exploration, system level design, triple play, customer premises equipment, quality of service

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